1. Field Of The Invention
This invention relates to memory arrays and, more particularly, to methods and apparatus for enabling the failure rate testing of flash electrically erasable programmable read only memories (flash EEPROMs).
2. History Of The Prior Art
Modern computer systems make extensive use of long term memory. Typically this memory is provided by one or more electro-mechanical hard (fixed) disk drives constructed of flat circular magnetic disks which rotate about a central axis and which have a mechanical arm to write to read from positions on the magnetic disk. Hard disk drives are very useful and have become almost a necessity to the operation of personal computers. However, such electro-mechanical drives are relatively heavy, require a significant amount of space within a computer, require a significant amount of the power in use, and are very susceptible to shock. A hard drive within a portable computer which is dropped is quite likely to cease functioning with a catastrophic loss of data.
Recently, forms of long term storage other than electro-mechanical hard disk drives have become feasible for use in computers. One of these is flash EEPROM. A flash EEPROM memory array includes a large plurality of floating-gate field effect transistors arranged as memory cells in typical row and column fashion with circuitry for accessing the individual cells and placing the memory transistors of those cells in one of two memory conditions. A flash memory cell, like a typical EPROM cell retains information when power is removed.
Flash EEPROM memory has a number of characteristics which adapt it to use as long term memory. It is light in weight, occupies very little space, and consumes less power than electro-mechanical disk drives. More importantly, it is especially rugged. It will withstand without adverse effects repeated drops each of which would destroy a typical electro-mechanical hard disk drive.
A peculiarity of flash EEPROM is that it is erased by applying a high voltage simultaneously to the source terminals of all of the transistors (cells) used in the memory. Because these source terminals are all connected to one another by metallic busing in the array, the entire array (or some subportion thereof) must be erased at once. While an electro-mechanical hard disk will typically store information in a first area of the disk and then rewrite that same area of the disk when the information changes, this is not possible with a flash EEPROM memory array without erasing all of the valid information that remains in the array along with the invalid (dirty) information.
Because of this, one new architecture used for programming and erasing sectors of a flash EEPROM array divides the entire array into smaller separately erasable blocks so that when a block is erased the amount of valid data which must be reprogrammed is reduced. Then, when the information at a data entry changes, the changed information is written to a new sector on an available block rather than written over the old data; and the old data is marked dirty. This allows erasure to be delayed until a large number of dirty sectors have accumulated on a block so that the number of erasure operations is reduced to a minimum. When erasure occurs, all of the valid data in the block to be erased is written to a new block; and then the dirty block is erased and put back in use as a clean block of memory.
This architecture requires that there always be a significant amount of free memory available to store the changing data and to provide room to store the valid data removed from any dirty block during a cleanup operation. This places a significant burden on the memory array. Whereas it is possible for an electro-mechanical hard disk drive to merely mark bad sectors and avoid them, flash EEPROM arrays must keep memory available for use even though that memory may have experienced some forms of data failure. For this reason various circuitry and software processes are utilized to render flash EEPROM as failure proof as possible. In fact, flash EEPROM memory arrays are now estimated to be so fail proof that it has become extremely expensive to test such arrays to determine their failure characteristics.